DPC++ Runtime
Runtime libraries for oneAPI DPC++
common.hpp File Reference
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Classes

struct  cl::__ESIMD_ENS::detail::lsc_expand_type< T >
 
struct  cl::__ESIMD_ENS::detail::lsc_bitcast_type< T >
 
class  cl::__ESIMD_ENS::detail::cache_hint_wrap< Hint >
 

Namespaces

 cl
 We provide new interfaces for matrix muliply in this patch:
 
 cl::__ESIMD_ENS
 
 cl::__ESIMD_ENS::detail
 

Enumerations

enum  cl::__ESIMD_ENS::argument_type {
  cl::__ESIMD_ENS::argument_type::U1 = 0, cl::__ESIMD_ENS::argument_type::S1 = 1, cl::__ESIMD_ENS::argument_type::U2 = 2, cl::__ESIMD_ENS::argument_type::S2 = 3,
  cl::__ESIMD_ENS::argument_type::U4 = 4, cl::__ESIMD_ENS::argument_type::S4 = 5, cl::__ESIMD_ENS::argument_type::U8 = 6, cl::__ESIMD_ENS::argument_type::S8 = 7,
  cl::__ESIMD_ENS::argument_type::BF16 = 8, cl::__ESIMD_ENS::argument_type::FP16 = 9, cl::__ESIMD_ENS::argument_type::TF32 = 11
}
 
enum  cl::__ESIMD_ENS::lsc_scope : uint8_t {
  cl::__ESIMD_ENS::lsc_scope::group = 0, cl::__ESIMD_ENS::lsc_scope::local = 1, cl::__ESIMD_ENS::lsc_scope::tile = 2, cl::__ESIMD_ENS::lsc_scope::gpu = 3,
  cl::__ESIMD_ENS::lsc_scope::gpus = 4, cl::__ESIMD_ENS::lsc_scope::system = 5, cl::__ESIMD_ENS::lsc_scope::sysacq = 6
}
 The scope that lsc_fence operation should apply to Supported platforms: DG2, PVC. More...
 
enum  cl::__ESIMD_ENS::lsc_fence_op : uint8_t {
  cl::__ESIMD_ENS::lsc_fence_op::none = 0, cl::__ESIMD_ENS::lsc_fence_op::evict = 1, cl::__ESIMD_ENS::lsc_fence_op::invalidate = 2, cl::__ESIMD_ENS::lsc_fence_op::discard = 3,
  cl::__ESIMD_ENS::lsc_fence_op::clean = 4, cl::__ESIMD_ENS::lsc_fence_op::flushl3 = 5
}
 The lsc_fence operation to apply to caches Supported platforms: DG2, PVC. More...
 
enum  cl::__ESIMD_ENS::lsc_memory_kind : uint8_t { cl::__ESIMD_ENS::lsc_memory_kind::untyped_global = 0, cl::__ESIMD_ENS::lsc_memory_kind::untyped_global_low_pri = 1, cl::__ESIMD_ENS::lsc_memory_kind::typed_global = 2, cl::__ESIMD_ENS::lsc_memory_kind::shared_local = 3 }
 The specific LSC shared function to fence with lsc_fence Supported platforms: DG2, PVC. More...
 
enum  cl::__ESIMD_ENS::lsc_data_size : uint8_t {
  cl::__ESIMD_ENS::lsc_data_size::default_size = 0, cl::__ESIMD_ENS::lsc_data_size::u8 = 1, cl::__ESIMD_ENS::lsc_data_size::u16 = 2, cl::__ESIMD_ENS::lsc_data_size::u32 = 3,
  cl::__ESIMD_ENS::lsc_data_size::u64 = 4, cl::__ESIMD_ENS::lsc_data_size::u8u32 = 5, cl::__ESIMD_ENS::lsc_data_size::u16u32 = 6, cl::__ESIMD_ENS::lsc_data_size::u16u32h = 7
}
 Data size or format to read or store. More...
 
enum  cl::__ESIMD_ENS::detail::lsc_atomic_op : uint8_t {
  cl::__ESIMD_ENS::detail::lsc_atomic_op::iinc = 0x08, cl::__ESIMD_ENS::detail::lsc_atomic_op::idec = 0x09, cl::__ESIMD_ENS::detail::lsc_atomic_op::load = 0x0a, cl::__ESIMD_ENS::detail::lsc_atomic_op::store = 0x0b,
  cl::__ESIMD_ENS::detail::lsc_atomic_op::iadd = 0x0c, cl::__ESIMD_ENS::detail::lsc_atomic_op::isub = 0x0d, cl::__ESIMD_ENS::detail::lsc_atomic_op::smin = 0x0e, cl::__ESIMD_ENS::detail::lsc_atomic_op::smax = 0x0f,
  cl::__ESIMD_ENS::detail::lsc_atomic_op::umin = 0x10, cl::__ESIMD_ENS::detail::lsc_atomic_op::umax = 0x11, cl::__ESIMD_ENS::detail::lsc_atomic_op::icas = 0x12, cl::__ESIMD_ENS::detail::lsc_atomic_op::fadd = 0x13,
  cl::__ESIMD_ENS::detail::lsc_atomic_op::fsub = 0x14, cl::__ESIMD_ENS::detail::lsc_atomic_op::fmin = 0x15, cl::__ESIMD_ENS::detail::lsc_atomic_op::fmax = 0x16, cl::__ESIMD_ENS::detail::lsc_atomic_op::fcas = 0x17,
  cl::__ESIMD_ENS::detail::lsc_atomic_op::bit_and = 0x18, cl::__ESIMD_ENS::detail::lsc_atomic_op::bit_or = 0x19, cl::__ESIMD_ENS::detail::lsc_atomic_op::bit_xor = 0x1a
}
 LSC atomic operations op codes. More...
 
enum  cl::__ESIMD_ENS::detail::lsc_vector_size : uint8_t {
  cl::__ESIMD_ENS::detail::lsc_vector_size::n1 = 1, cl::__ESIMD_ENS::detail::lsc_vector_size::n2 = 2, cl::__ESIMD_ENS::detail::lsc_vector_size::n3 = 3, cl::__ESIMD_ENS::detail::lsc_vector_size::n4 = 4,
  cl::__ESIMD_ENS::detail::lsc_vector_size::n8 = 5, cl::__ESIMD_ENS::detail::lsc_vector_size::n16 = 6, cl::__ESIMD_ENS::detail::lsc_vector_size::n32 = 7, cl::__ESIMD_ENS::detail::lsc_vector_size::n64 = 8
}
 
enum  cl::__ESIMD_ENS::detail::lsc_data_order : uint8_t { cl::__ESIMD_ENS::detail::lsc_data_order::nontranspose = 1, cl::__ESIMD_ENS::detail::lsc_data_order::transpose = 2 }
 
enum  cl::__ESIMD_ENS::cache_hint : uint8_t {
  cl::__ESIMD_ENS::cache_hint::none = 0, cl::__ESIMD_ENS::cache_hint::uncached = 1, cl::__ESIMD_ENS::cache_hint::cached = 2, cl::__ESIMD_ENS::cache_hint::write_back = 3,
  cl::__ESIMD_ENS::cache_hint::write_through = 4, cl::__ESIMD_ENS::cache_hint::streaming = 5, cl::__ESIMD_ENS::cache_hint::read_invalidate = 6
}
 L1 or L3 cache hint kinds. More...
 
enum  cl::__ESIMD_ENS::detail::lsc_action { cl::__ESIMD_ENS::detail::lsc_action::prefetch, cl::__ESIMD_ENS::detail::lsc_action::load, cl::__ESIMD_ENS::detail::lsc_action::store, cl::__ESIMD_ENS::detail::lsc_action::atomic }
 
enum  cl::__ESIMD_ENS::split_barrier_action : uint8_t { cl::__ESIMD_ENS::split_barrier_action::wait = 0, cl::__ESIMD_ENS::split_barrier_action::signal = 1 }
 Represents a split barrier action. More...
 

Functions

template<lsc_vector_size VS>
constexpr void cl::__ESIMD_ENS::detail::check_lsc_vector_size ()
 
template<typename T , lsc_data_size DS>
constexpr void cl::__ESIMD_ENS::detail::check_lsc_data_size ()
 
template<__ESIMD_NS::atomic_op Op>
constexpr void cl::__ESIMD_ENS::detail::check_lsc_atomic_op ()
 
template<__ESIMD_NS::atomic_op Op, unsigned NumSrc>
constexpr void cl::__ESIMD_ENS::detail::check_lsc_atomic ()
 Check the legality of lsc xatomic call in terms of size and type. More...
 
template<__ESIMD_NS::atomic_op Op>
constexpr lsc_atomic_op cl::__ESIMD_ENS::detail::to_lsc_atomic_op ()
 
template<lsc_vector_size VS>
constexpr uint8_t cl::__ESIMD_ENS::detail::to_int ()
 
template<uint8_t VS>
constexpr lsc_vector_size cl::__ESIMD_ENS::detail::to_lsc_vector_size ()
 
template<typename T , lsc_data_size DS>
constexpr lsc_data_size cl::__ESIMD_ENS::detail::finalize_data_size ()
 
constexpr lsc_data_size cl::__ESIMD_ENS::detail::expand_data_size (lsc_data_size DS)
 
constexpr bool cl::__ESIMD_ENS::detail::are_both (cache_hint First, cache_hint Second, cache_hint Val)
 
template<lsc_action Action, cache_hint L1, cache_hint L3>
constexpr void cl::__ESIMD_ENS::detail::check_lsc_cache_hint ()