DPC++ Runtime
Runtime libraries for oneAPI DPC++
fpga_reg.hpp
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1 //==-------------- fpga_reg.hpp --- SYCL FPGA Reg Extensions ---------------==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #pragma once
10 
12 #include <type_traits>
13 
15 namespace sycl {
16 namespace ext {
17 namespace intel {
18 
19 // Returns a registered copy of the input
20 // This function is intended for FPGA users to instruct the compiler to insert
21 // at least one register stage between the input and the return value.
22 template <typename _T>
23 typename std::enable_if<std::is_trivially_copyable<_T>::value, _T>::type
24 fpga_reg(_T t) {
25 #if __has_builtin(__builtin_intel_fpga_reg)
26  return __builtin_intel_fpga_reg(t);
27 #else
28  return t;
29 #endif
30 }
31 
32 template <typename _T>
33 [[deprecated(
34  "ext::intel::fpga_reg will only support trivially_copyable types in a "
35  "future release. The type used here will be disallowed.")]]
36 typename std::enable_if<std::is_trivially_copyable<_T>::value == false,
37  _T>::type
38 fpga_reg(_T t) {
39 #if __has_builtin(__builtin_intel_fpga_reg)
40  return __builtin_intel_fpga_reg(t);
41 #else
42  return t;
43 #endif
44 }
45 
46 } // namespace intel
47 } // namespace ext
48 
49 } // namespace sycl
50 } // __SYCL_INLINE_NAMESPACE(cl)
51 
52 // Keep it consistent with FPGA attributes like intelfpga::memory()
53 // Currently clang does not support nested namespace for attributes
54 namespace intelfpga {
55 template <typename _T>
56 [[deprecated("intelfpga::fpga_reg will be removed in a future release.")]] _T
57 fpga_reg(const _T &t) {
59 }
60 } // namespace intelfpga
intelfpga::fpga_reg
_T fpga_reg(const _T &t)
Definition: fpga_reg.hpp:57
sycl
Definition: invoke_simd.hpp:68
intelfpga
Definition: fpga_reg.hpp:54
defines.hpp
cl
We provide new interfaces for matrix muliply in this patch:
Definition: access.hpp:13
cl::sycl::ext::intel::fpga_reg
std::enable_if< std::is_trivially_copyable< _T >::value, _T >::type fpga_reg(_T t)
Definition: fpga_reg.hpp:24
__SYCL_INLINE_NAMESPACE
#define __SYCL_INLINE_NAMESPACE(X)
Definition: defines_elementary.hpp:12