common.hpp File Reference

#include <sycl/detail/defines.hpp>
#include <sycl/exception.hpp>
#include <sycl/ext/intel/esimd/detail/defines_elementary.hpp>
#include <sycl/ext/intel/esimd/native/common.hpp>
#include <cstdint>
#include <type_traits>

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Classes
struct	sycl::_V1::ext::intel::esimd::saturation_on_tag
	Gen hardware supports applying saturation to results of certain operations. More...
struct	sycl::_V1::ext::intel::esimd::saturation_off_tag
	This type tag represents "saturation off" behavior. More...
struct	sycl::_V1::ext::intel::esimd::detail::LocalAccessorMarker
struct	sycl::_V1::ext::intel::esimd::detail::is_saturation_tag< T >
class	sycl::_V1::ext::intel::esimd::detail::cache_hint_wrap< Hint >
struct	sycl::_V1::ext::intel::esimd::detail::lsc_expand_type< T >

Namespaces
	sycl
	sycl::_V1
	sycl::_V1::ext
	sycl::_V1::ext::intel
	sycl::_V1::ext::intel::esimd
	sycl::_V1::ext::intel::esimd::detail

Typedefs
using	sycl::_V1::ext::intel::esimd::uchar = unsigned char
using	sycl::_V1::ext::intel::esimd::ushort = unsigned short
using	sycl::_V1::ext::intel::esimd::uint = unsigned int
using	sycl::_V1::ext::intel::esimd::SurfaceIndex = unsigned int
	Surface index type. More...

Enumerations
enum	sycl::_V1::ext::intel::esimd::rgba_channel : uint8_t { sycl::_V1::ext::intel::esimd::rgba_channel::R, sycl::_V1::ext::intel::esimd::rgba_channel::G, sycl::_V1::ext::intel::esimd::rgba_channel::B, sycl::_V1::ext::intel::esimd::rgba_channel::A }
	Represents a pixel's channel. More...
enum	sycl::_V1::ext::intel::esimd::raw_send_eot : uint8_t { sycl::_V1::ext::intel::esimd::raw_send_eot::not_eot = 0, sycl::_V1::ext::intel::esimd::raw_send_eot::eot = 1 }
	Specify if end of thread should be set. More...
enum	sycl::_V1::ext::intel::esimd::raw_send_sendc : uint8_t { sycl::_V1::ext::intel::esimd::raw_send_sendc::not_sendc = 0, sycl::_V1::ext::intel::esimd::raw_send_sendc::sendc = 1 }
	Specify if sendc should be used. More...
enum	sycl::_V1::ext::intel::esimd::rgba_channel_mask : uint8_t {   sycl::_V1::ext::intel::esimd::rgba_channel_mask::R = detail::chR, sycl::_V1::ext::intel::esimd::rgba_channel_mask::G = detail::chG, sycl::_V1::ext::intel::esimd::rgba_channel_mask::GR = detail::chG | detail::chR, sycl::_V1::ext::intel::esimd::rgba_channel_mask::B = detail::chB,   sycl::_V1::ext::intel::esimd::rgba_channel_mask::BR = detail::chB | detail::chR, sycl::_V1::ext::intel::esimd::rgba_channel_mask::BG = detail::chB | detail::chG, sycl::_V1::ext::intel::esimd::rgba_channel_mask::BGR = detail::chB | detail::chG | detail::chR, sycl::_V1::ext::intel::esimd::rgba_channel_mask::A = detail::chA,   sycl::_V1::ext::intel::esimd::rgba_channel_mask::AR = detail::chA | detail::chR, sycl::_V1::ext::intel::esimd::rgba_channel_mask::AG = detail::chA | detail::chG, sycl::_V1::ext::intel::esimd::rgba_channel_mask::AGR = detail::chA | detail::chG | detail::chR, sycl::_V1::ext::intel::esimd::rgba_channel_mask::AB = detail::chA | detail::chB,   sycl::_V1::ext::intel::esimd::rgba_channel_mask::ABR = detail::chA | detail::chB | detail::chR, sycl::_V1::ext::intel::esimd::rgba_channel_mask::ABG = detail::chA | detail::chB | detail::chG, sycl::_V1::ext::intel::esimd::rgba_channel_mask::ABGR = detail::chA | detail::chB | detail::chG | detail::chR }
	Represents a pixel's channel mask - all possible combinations of enabled channels. More...
enum	sycl::_V1::ext::intel::esimd::atomic_op : uint8_t {   sycl::_V1::ext::intel::esimd::atomic_op::add = 0x0, sycl::_V1::ext::intel::esimd::atomic_op::sub = 0x1, sycl::_V1::ext::intel::esimd::atomic_op::inc = 0x2, sycl::_V1::ext::intel::esimd::atomic_op::dec = 0x3,   sycl::_V1::ext::intel::esimd::atomic_op::umin = 0x4, sycl::_V1::ext::intel::esimd::atomic_op::umax = 0x5, sycl::_V1::ext::intel::esimd::atomic_op::xchg = 0x6, sycl::_V1::ext::intel::esimd::atomic_op::cmpxchg = 0x7,   sycl::_V1::ext::intel::esimd::atomic_op::bit_and = 0x8, sycl::_V1::ext::intel::esimd::atomic_op::bit_or = 0x9, sycl::_V1::ext::intel::esimd::atomic_op::bit_xor = 0xa, sycl::_V1::ext::intel::esimd::atomic_op::smin = 0xb,   sycl::_V1::ext::intel::esimd::atomic_op::smax = 0xc, sycl::_V1::ext::intel::esimd::atomic_op::fmax = 0x10, sycl::_V1::ext::intel::esimd::atomic_op::fmin = 0x11, sycl::_V1::ext::intel::esimd::atomic_op::fcmpxchg = 0x12,   sycl::_V1::ext::intel::esimd::atomic_op::fcmpwr = fcmpxchg, sycl::_V1::ext::intel::esimd::atomic_op::fadd = 0x13, sycl::_V1::ext::intel::esimd::atomic_op::fsub = 0x14, sycl::_V1::ext::intel::esimd::atomic_op::load = 0x15,   sycl::_V1::ext::intel::esimd::atomic_op::store = 0x16, sycl::_V1::ext::intel::esimd::atomic_op::predec = 0xff }
	Represents an atomic operation. More...
enum	sycl::_V1::ext::intel::esimd::cache_hint : uint8_t {   sycl::_V1::ext::intel::esimd::cache_hint::none = 0, sycl::_V1::ext::intel::esimd::cache_hint::uncached = 1, sycl::_V1::ext::intel::esimd::cache_hint::cached = 2, sycl::_V1::ext::intel::esimd::cache_hint::write_back = 3,   sycl::_V1::ext::intel::esimd::cache_hint::write_through = 4, sycl::_V1::ext::intel::esimd::cache_hint::streaming = 5, sycl::_V1::ext::intel::esimd::cache_hint::read_invalidate = 6, sycl::_V1::ext::intel::esimd::cache_hint::const_cached = 7 }
	L1, L2 or L3 cache hints. More...
enum	sycl::_V1::ext::intel::esimd::fence_scope : uint8_t {   sycl::_V1::ext::intel::esimd::fence_scope::group = 0, sycl::_V1::ext::intel::esimd::fence_scope::local = 1, sycl::_V1::ext::intel::esimd::fence_scope::tile = 2, sycl::_V1::ext::intel::esimd::fence_scope::gpu = 3,   sycl::_V1::ext::intel::esimd::fence_scope::gpus = 4, sycl::_V1::ext::intel::esimd::fence_scope::system = 5, sycl::_V1::ext::intel::esimd::fence_scope::system_acquire = 6 }
	The scope that fence() operation should apply to. More...
enum	sycl::_V1::ext::intel::esimd::fence_flush_op : uint8_t { sycl::_V1::ext::intel::esimd::fence_flush_op::none = 0, sycl::_V1::ext::intel::esimd::fence_flush_op::evict = 1, sycl::_V1::ext::intel::esimd::fence_flush_op::invalidate = 2, sycl::_V1::ext::intel::esimd::fence_flush_op::clean = 4 }
	The cache flush operation to apply to caches after fence() is complete. More...
enum	sycl::_V1::ext::intel::esimd::memory_kind : uint8_t { sycl::_V1::ext::intel::esimd::memory_kind::global = 0, sycl::_V1::ext::intel::esimd::memory_kind::image = 2, sycl::_V1::ext::intel::esimd::memory_kind::local = 3 }
	The target memory kind for fence() operation. More...
enum	sycl::_V1::ext::intel::esimd::cache_level : uint8_t { sycl::_V1::ext::intel::esimd::cache_level::L1 = 1, sycl::_V1::ext::intel::esimd::cache_level::L2 = 2, sycl::_V1::ext::intel::esimd::cache_level::L3 = 3 }
	L1, L2 or L3 cache hint levels. L3 is reserved for future use. More...
enum	sycl::_V1::ext::intel::esimd::detail::lsc_data_size : uint8_t {   sycl::_V1::ext::intel::esimd::detail::lsc_data_size::default_size = 0, sycl::_V1::ext::intel::esimd::detail::lsc_data_size::u8 = 1, sycl::_V1::ext::intel::esimd::detail::lsc_data_size::u16 = 2, sycl::_V1::ext::intel::esimd::detail::lsc_data_size::u32 = 3,   sycl::_V1::ext::intel::esimd::detail::lsc_data_size::u64 = 4, sycl::_V1::ext::intel::esimd::detail::lsc_data_size::u8u32 = 5, sycl::_V1::ext::intel::esimd::detail::lsc_data_size::u16u32 = 6, sycl::_V1::ext::intel::esimd::detail::lsc_data_size::u16u32h = 7 }
	Data size or format to read or store. More...
enum	sycl::_V1::ext::intel::esimd::detail::lsc_vector_size : uint8_t {   sycl::_V1::ext::intel::esimd::detail::lsc_vector_size::n1 = 1, sycl::_V1::ext::intel::esimd::detail::lsc_vector_size::n2 = 2, sycl::_V1::ext::intel::esimd::detail::lsc_vector_size::n3 = 3, sycl::_V1::ext::intel::esimd::detail::lsc_vector_size::n4 = 4,   sycl::_V1::ext::intel::esimd::detail::lsc_vector_size::n8 = 5, sycl::_V1::ext::intel::esimd::detail::lsc_vector_size::n16 = 6, sycl::_V1::ext::intel::esimd::detail::lsc_vector_size::n32 = 7, sycl::_V1::ext::intel::esimd::detail::lsc_vector_size::n64 = 8 }
enum	sycl::_V1::ext::intel::esimd::detail::lsc_data_order : uint8_t { sycl::_V1::ext::intel::esimd::detail::lsc_data_order::nontranspose = 1, sycl::_V1::ext::intel::esimd::detail::lsc_data_order::transpose = 2 }
enum	sycl::_V1::ext::intel::esimd::detail::cache_action { sycl::_V1::ext::intel::esimd::detail::cache_action::prefetch, sycl::_V1::ext::intel::esimd::detail::cache_action::load, sycl::_V1::ext::intel::esimd::detail::cache_action::store, sycl::_V1::ext::intel::esimd::detail::cache_action::atomic }

Functions
constexpr ESIMD_INLINE bool	sycl::_V1::ext::intel::esimd::detail::isPowerOf2 (unsigned int n)
	Check if a given 32 bit positive integer is a power of 2 at compile time. More...
constexpr ESIMD_INLINE bool	sycl::_V1::ext::intel::esimd::detail::isPowerOf2 (unsigned int n, unsigned int limit)
	Check at compile time if given 32 bit positive integer is both: More...
constexpr int	sycl::_V1::ext::intel::esimd::is_channel_enabled (rgba_channel_mask M, rgba_channel Ch)
constexpr int	sycl::_V1::ext::intel::esimd::get_num_channels_enabled (rgba_channel_mask M)
template<sycl::ext::intel::esimd::atomic_op Op>
constexpr bool	sycl::_V1::ext::intel::esimd::detail::has_lsc_equivalent ()
template<sycl::ext::intel::esimd::atomic_op Op>
constexpr sycl::ext::intel::esimd::native::lsc::atomic_op	sycl::_V1::ext::intel::esimd::detail::to_lsc_atomic_op ()
template<sycl::ext::intel::esimd::native::lsc::atomic_op Op>
constexpr sycl::ext::intel::esimd::atomic_op	sycl::_V1::ext::intel::esimd::detail::to_atomic_op ()
template<sycl::ext::intel::esimd::atomic_op Op>
constexpr int	sycl::_V1::ext::intel::esimd::detail::get_num_args ()
template<typename T , lsc_data_size DS>
constexpr void	sycl::_V1::ext::intel::esimd::detail::check_lsc_data_size ()
template<typename T , lsc_data_size DS>
constexpr lsc_data_size	sycl::_V1::ext::intel::esimd::detail::finalize_data_size ()
template<int VS>
constexpr void	sycl::_V1::ext::intel::esimd::detail::check_lsc_vector_size ()
template<lsc_vector_size VS>
constexpr uint8_t	sycl::_V1::ext::intel::esimd::detail::to_int ()
template<int VS>
constexpr lsc_vector_size	sycl::_V1::ext::intel::esimd::detail::to_lsc_vector_size ()
constexpr bool	sycl::_V1::ext::intel::esimd::detail::are_both (cache_hint First, cache_hint Second, cache_hint Val)
template<cache_action Action, cache_hint L1Hint, cache_hint L2Hint>
void	sycl::_V1::ext::intel::esimd::detail::check_cache_hint ()
constexpr lsc_data_size	sycl::_V1::ext::intel::esimd::detail::expand_data_size (lsc_data_size DS)

Variables
static constexpr saturation_off_tag	sycl::_V1::ext::intel::esimd::saturation_off {}
	Type tag object representing "saturation off" behavior. More...
static constexpr saturation_on_tag	sycl::_V1::ext::intel::esimd::saturation_on {}
	Type tag object representing "saturation on" behavior. More...
template<class T >
constexpr bool	sycl::_V1::ext::intel::esimd::detail::is_saturation_tag_v = is_saturation_tag<T>::value
template<rgba_channel Ch>
static constexpr uint8_t	sycl::_V1::ext::intel::esimd::detail::ch = 1 << static_cast<int>(Ch)
static constexpr uint8_t	sycl::_V1::ext::intel::esimd::detail::chR = ch<rgba_channel::R>
static constexpr uint8_t	sycl::_V1::ext::intel::esimd::detail::chG = ch<rgba_channel::G>
static constexpr uint8_t	sycl::_V1::ext::intel::esimd::detail::chB = ch<rgba_channel::B>
static constexpr uint8_t	sycl::_V1::ext::intel::esimd::detail::chA = ch<rgba_channel::A>
static constexpr SurfaceIndex	sycl::_V1::ext::intel::esimd::detail::SLM_BTI = 254
static constexpr SurfaceIndex	sycl::_V1::ext::intel::esimd::detail::INVALID_BTI